High-g mounting arrangement for electronic chip carrier

ABSTRACT

A chip carrier is coupled to a printed circuit board by leads so that the chip carrier stands off from the printed circuit board. A spacer is provided between the chip carrier and the printed circuit board. The spacer reduces g forces on the leads.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a mounting arrangement for anelectronic chip carrier.

BACKGROUND OF THE INVENTION AND PRIOR ART

[0002] Chip carriers, such as ceramic chip carriers, are used to enclosesensitive electronic devices that must function in difficultenvironments such as vacuums. Some applications, such as gun-launchedelectronics, subject the chip carrier to substantial acceleration forces(g's) of more than 7000 g's.

[0003] A standard mounting arrangement for mounting a chip carrier 10 toa printed circuit board 12 is shown in FIG. 1. The chip carrier 10,which may be a ceramic chip carrier, is mounted to the printed circuitboard 12 by a plurality of J leads 14. The J leads 14 may be copper or acopper alloy and are suitably coupled such as by braising or solderingto the electronics contained within the chip carrier 10. The J leads 14are also coupled such as by soldering to appropriate elements of theprinted circuit board 12.

[0004] As can be seen from FIG. 1, the chip carrier 10 is supportedabove the printed circuit board 12 by the J leads 14. This mountingarrangement shown in FIG. 1 accommodates mismatches in coefficients ofthermal expansion between the chip carrier 10 and the printed circuitboard 12. However, the J leads 14 for the chip carrier 10 will notadequately support the chip carrier 10 when subjected to the very highaccelerations of some applications such as gun-launch applications.

[0005] For example, the chip carrier 10 may weigh as little as one gram.However, at an acceleration of 10,000 times gravity (10,000 g's), thechip carrier 10 effectively weighs ten kilograms (or twenty-two pounds).That acceleration force can occur in a normal direction, in a sheardirection, or in any combination of normal and shear directions relativeto the printed circuit board 12. At one gram, the chip carrier 10 mayhave as many as twenty of the J leads 14 each of which is 0.008 by 0.025inches in cross-section. At 10,000 g's, this arrangement results in5,500 pounds per square inch in shear on the J leads 14, causing the Jleads 14 to fail and allow separation between the chip carrier 10 andthe printed circuit board 12.

[0006] The present invention is directed to an arrangement whichovercomes one or more of these or other problems of the prior art.

SUMMARY OF THE INVENTION

[0007] In accordance with one aspect of the present invention, amounting arrangement comprises a chip carrier, a mounting structure, anda spacer. The spacer is between the chip carrier and the mountingstructure, and the spacer has dimensions so as to transfer g forces fromthe chip carrier to the mounting structure.

[0008] In accordance with another aspect of the present invention, amounting arrangement comprises a chip carrier, a mounting structure,leads, and a spacer. The leads couple the chip carrier to the mountingstructure so that the chip carrier stands off from the mountingstructure. The spacer is between the chip carrier and the mountingstructure, and the spacer reduces g forces on the leads.

[0009] In accordance with still another aspect of the present invention,a method of mounting a chip carrier to a mounting structure comprisesbonding a spacer to the chip carrier, and bonding the spacer to themounting structure. The spacer is arranged to transfer g forces from thechip carrier to the mounting structure.

[0010] In accordance with a further aspect of the present invention, anassembly comprises a chip carrier, a mounting structure, leads, and aforce diverter. The leads are electrically coupled to the chip carrierand to the mounting structure. The force diverter is mechanicallycoupled to the chip carrier and to the mounting structure, and the forcediverter is arranged to divert force generated by the chip carrier fromthe leads and to the mounting structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] These and other features and advantages will become more apparentfrom a detailed consideration of the invention when taken in conjunctionwith the drawings in which:

[0012]FIG. 1 is a cross-sectional side view of a prior art mountingarrangement for mounting a chip carrier to a printed circuit board;

[0013]FIG. 2 is a cross-sectional side view of a mounting arrangementfor mounting a chip carrier to a mounting support, such as a printedcircuit board, according to an embodiment of the present invention; and,

[0014]FIG. 3 is a reproduction of FIG. 2 showing dimensions useful inpresenting an example of the present invention.

DETAILED DESCRIPTION

[0015] As shown in FIG. 2, a chip carrier 20 is mounted to a printedcircuit board 22 by a plurality of J leads 24. The chip carrier 20, forexample, may be ceramic such as an alumina mixture having a coefficientof thermal expansion on the order of 6×10⁻⁶ in/in-degree-C. The J leads24, for example, may be copper or a copper alloy having a coefficient ofthermal expansion on the order of 18×10⁻⁶ in/in-degree-C. The J leads 24are suitably coupled to the electronics contained within the chipcarrier 20. For example, the J leads 24 may be braised or soldered tocontacts extending into the chip carrier 20. The J leads 24 are alsoelectrically coupled such as by soldering to appropriate elements of theprinted circuit board 22.

[0016] Unlike the prior mounting arrangement shown in FIG. 1, the chipcarrier 20 is not solely supported above the printed circuit board 22 bythe J leads 24. Instead, a spacer 26 is provided between the chipcarrier 20 and the printed circuit board 22. The spacer 26 may be heldin place by a first adhesive layer 28 bonding the spacer 26 to the chipcarrier 20 and a second adhesive layer 30 bonding the spacer 26 to theprinted circuit board 22. The adhesive of the first and second adhesivelayers 28 and 30, for example, may be epoxy having a coefficient ofthermal expansion on the order of 50×10⁻⁶ in/in-degree-C. Accordingly,the spacer 26 diverts at least enough of the forces exerted on the chipcarrier 20 during accelerations in order to protect the J leads 24coupled between the chip carrier 20 and the printed circuit board 22.That is, the spacer 26 reduces the per square inch force exerted on theJ leads 24.

[0017] The mounting arrangement shown in FIG. 2 preferably matches thecoefficients of thermal expansion of the materials that are used for thechip carrier 20, the J leads 24, and the spacer 26, and the first andsecond adhesive layers 28 and 30. For given of materials for the chipcarrier 20 and the J leads 24, the materials for the spacer 26 and forthe first and second adhesive layers 28 and 30 are selected in order toprovide a match for these coefficients of thermal expansion. Forexample, if ceramic is used for the chip carrier 20 and copper or acopper alloy is used for the J leads 24, then ceramic may be chosen forthe spacer 26 and epoxy may be chosen for the adhesive in the first andsecond adhesive layers 28 and 30. In this case, the coefficient ofthermal expansion of ceramic is less that the coefficient of thermalexpansion of copper which is less than the coefficient of thermalexpansion of epoxy.

[0018] Assuming that the materials as described immediately above areused, the relative thicknesses of the spacer 26 and of the first andsecond adhesive layers 28 and 30 may be calculated using a threedimensional finite element analysis of the expansion properties due tothe varying vertical and horizontal expansion coefficients of the epoxywhen constrained by the lower coefficients of thermal expansion of theceramic and of the material of the printed circuit board 22. There willalways be a solution to this analysis because the coefficient of thermalexpansion of ceramic is less that the coefficient of thermal expansionof copper which is less than the coefficient of thermal expansion ofepoxy.

[0019] A simplified form of the equations which must be solved using afinite element analysis are given as follows:

(h _(Cu))(CTE _(Cu))=(h _(ceramic))(CTE _(ceramic))+(h _(epoxy))(CTE_(epoxy))  (1)

h _(Cu) =h _(ceramic) +h _(epoxy)  (2)

[0020] where h is a dimension of the material, where CTE is coefficientof thermal expansion, and where Cu is copper. Accordingly, h_(epoxy) inequations (1) and (2) is the combined thickness of the first and secondadhesive layers 28 and 30, h_(ceramic) is the thickness of the spacer26, and h_(Cu) is the length of the J leads 24 between the lower edge ofthe spacer 26, as viewed in FIG. 2, and the upper surface of the printedcircuit board 22. Exemplary dimensions are shown in FIG. 3. Therefore,given the materials for the first and second adhesive layers 28 and 30,the spacer 26, and the J leads 24, the three dimensional finite elementanalysis represented by equations (1) and (2) determines the dimensionsof these devices.

[0021] For example, let it be assumed that the length of the J-leads 24between the lower edge of the spacer 26 and the upper surface of theprinted circuit board 22 is 0.070 inches, and let it be assumed that Xis the as yet unknown thickness of the spacer 26 required to equalizethe thermal expansion of the J leads 24 and the supporting spacer 26.Accordingly, h_(Cu) is 0.070 inches, h_(spacer) is X, and h_(epoxy) is(0.070−X) inches. Inserting these thicknesses and the CTE's of copper,ceramic, and epoxy into equation (1) produces that following equation:

(0.07)(18×10⁻⁶)=(X)(6×10⁻⁶)+(0.070−X)(50×10⁻⁶)

[0022] Solving for X produces X=0.050909, or approximately 0.051.Therefore, the total epoxy thickness must be (0.070-0.051) inches or0.019 inches.

[0023] The above example depends upon the use of ceramic for the spacer26, epoxy for the first and second adhesive layers 28 and 30, and copperfor the J leads 24. However, it is possible to use different materialsfor any or all of the J leads 24, the spacer 26, and the first and/orsecond adhesive layers 28 and 30. For example, the J leads 24 may becopper, the first and/or second adhesive layers 28 and 30 may be epoxy,but the spacer 26 may be a material other than ceramic so long as theCTE for the material selected for the spacer 26 satisfies the threedimensional finite element analysis and results in a reasonablethickness for the spacer 26.

[0024] Now, if the chip carrier 20 weighs one gram, and if the spacer 26provides a support surface for the chip carrier 20 that is 0.09 squareinches, a vertical acceleration of 10,000 times gravity results in thechip carrier 20 having an effective weight of ten kilograms (ortwenty-two pounds) producing a stress of 170 pounds per square inch onthe first and second adhesive layers 28 and 30. This stress is far lessthan the 6,000 pounds per square inch force produced by the arrangementshown in FIG. 1 and, if epoxy is used as the material for the first andsecond adhesive layers 28 and 30, is also well below the severalthousand pound per square inch limit for epoxy.

[0025] Moreover, by making the first adhesive layer 28 the thinnestpractical epoxy layer, the spacer 26 strengthens and stiffens the bottomof the chip carrier 20, and the resulting greater thickness of thesecond adhesive layer 30 better accommodates lateral expansiondifferences between the spacer 26 and the printed circuit board 22.

[0026] The use of the spacer 26 and the first and second adhesive layers28 and 30 permits a combination of high and low thermal expansionmaterials having thicknesses selected so that their combined thermalexpansion approximates the thermal expansion coefficient of the J leads24. Accordingly, bending of the J leads 24 and thermal stressing on thesolder joints of the J leads 24 are thereby minimized. Further, thespacer 26 provides structural support to accommodate the high mechanicalloads resulting from high accelerations on the chip carrier 20.Accordingly, failure of the J leads 24 during high g shocks is therebyavoided.

[0027] Certain modifications of the present invention have beendiscussed above. Other modifications will occur to those practicing inthe art of the present invention. For example, as described above, thechip carrier 20 is mounted to the printed circuit board 22. However, thechip carrier 20 may be mounted to support structures other than theprinted circuit board 22.

[0028] Also as described above, ceramic is chosen for the spacer 26 andepoxy is chosen for the adhesive in the first and second adhesive layers28 and 30 for the case where ceramic is used for the chip carrier 20 andcopper or a copper alloy is used for the J leads 24. However, materialsother than ceramic can be chosen for the spacer 26 and materials otherthan epoxy can be chosen for the adhesive in the first and secondadhesive layers 28 and 30 if a material other than ceramic is used forthe chip carrier 20 and/or if a material other than copper is used forthe J leads 24. Moreover, even where ceramic is used for the chipcarrier 20 and copper or a copper alloy is used for the J leads 24, amaterial other than ceramic can be chosen for the spacer 26 and amaterial other than epoxy can be chosen for the adhesive in the firstand second adhesive layers 28 and 30.

[0029] Furthermore, the chip carrier 20 is coupled to the printedcircuit board 22 by the J leads 24. However, leads other than J leadscan be used to couple the chip carrier 20 to the printed circuit board22.

[0030] Accordingly, the description of the present invention is to beconstrued as illustrative only and is for the purpose of teaching thoseskilled in the art the best mode of carrying out the invention. Thedetails may be varied substantially without departing from the spirit ofthe invention, and the exclusive use of all modifications which arewithin the scope of the appended claims is reserved.

What is claimed is:
 1. A mounting arrangement comprising: a chipcarrier; a mounting structure; and, a spacer between the chip carrierand the mounting structure, wherein the spacer has dimensions so as totransfer g forces from the chip carrier to the mounting structure. 2.The mounting arrangement of claim 1 wherein the chip carrier and thespacer are both ceramic.
 3. The mounting arrangement of claim 1 furthercomprising a first adhesive layer that bonds the spacer to the chipcarrier and a second adhesive layer that bonds the spacer to themounting structure.
 4. The mounting arrangement of claim 3 wherein thefirst adhesive layer is arranged to strengthen and stiffen the chipcarrier.
 5. The mounting arrangement of claim 3 wherein the spacer has afirst coefficient of thermal expansion, wherein at least one of thefirst and second adhesive layers has a second coefficient of thermalexpansion, and wherein the first coefficient of thermal expansion isless that the second coefficient of thermal expansion.
 6. The mountingarrangement of claim 3 wherein the chip carrier and the spacer are bothceramic.
 7. The mounting arrangement of claim 3 wherein the first andsecond adhesive layers are epoxy.
 8. The mounting arrangement of claim 7wherein the chip carrier and the spacer are both ceramic.
 9. Themounting arrangement of claim 8 wherein the ceramic of the spacer has afirst coefficient of thermal expansion, wherein the epoxy has a secondcoefficient of thermal expansion, and wherein the first coefficient ofthermal expansion is less that the second coefficient of thermalexpansion.
 10. The mounting arrangement of claim 1 wherein the spacer isceramic.
 11. The mounting arrangement of claim 1 wherein the mountingstructure is a printed circuit board.
 12. A mounting arrangementcomprising: a chip carrier; a mounting structure; leads that couple thechip carrier to the mounting structure so that the chip carrier standsoff from the mounting structure; and, a spacer between the chip carrierand the mounting structure, wherein the spacer reduces g forces on theleads.
 13. The mounting arrangement of claim 12 wherein the chip carrierand the spacer are both ceramic.
 14. The mounting arrangement of claim12 further comprising a first adhesive layer that bonds the spacer tothe chip carrier, and a second adhesive layer that bonds the spacer tothe mounting structure.
 15. The mounting arrangement of claim 14 whereinthe first adhesive layer is arranged to strengthen and stiffen the chipcarrier.
 16. The mounting arrangement of claim 14 wherein the spacer andthe first and second adhesive layers are selected so that thermalexpansions of the spacer and the first and second adhesive layerssubstantially match thermal expansion of the leads.
 17. The mountingarrangement of claim 14 wherein the spacer has a first coefficient ofthermal expansion CTE₁, wherein the leads have a second coefficient ofthermal expansion CTE₂, wherein the first and second adhesive layershave a third coefficient of thermal expansion CTE₃, and whereinCTE₁<CTE₂<CTE₃.
 18. The mounting arrangement of claim 14 wherein thechip carrier and the spacer are both ceramic.
 19. The mountingarrangement of claim 14 wherein the first and second adhesive layers areepoxy.
 20. The mounting arrangement of claim 19 wherein the chip carrierand the spacer are both ceramic.
 21. The mounting arrangement of claim20 wherein the ceramic of the spacer has a first coefficient of thermalexpansion CTE₁, wherein the leads have a second coefficient of thermalexpansion CTE₂, wherein the epoxy has a third coefficient of thermalexpansion CTE₃, and wherein CTE₁<CTE₂<CTE₃.
 22. The mounting arrangementof claim 12 wherein the mounting structure is a printed circuit board.23. The mounting arrangement of claim 12 wherein the spacer is ceramic.24. The mounting arrangement of claim 12 wherein the spacer is selectedso that thermal expansion of the spacer substantially matches thermalexpansion of the leads.
 25. A method of mounting a chip carrier to amounting structure comprising: bonding a spacer to the chip carrier;and, bonding the spacer to the mounting structure, wherein the spacer isarranged to transfer g forces from the chip carrier to the mountingstructure.
 26. The method of claim 25 wherein the chip carrier and thespacer are both ceramic.
 27. The method of claim 25 wherein the bondingof the spacer to the chip carrier comprises bonding the spacer to thechip carrier using a first adhesive layer, and wherein the bonding ofthe spacer to the mounting structure comprises bonding the spacer to themounting structure using a second adhesive layer.
 28. The method ofclaim 27 wherein the first adhesive layer is arranged to strengthen andstiffen the chip carrier.
 29. The method of claim 27 further comprisingcoupling the chip carrier to the mounting structure with electricalleads, wherein the spacer and the first and second adhesive layers areselected so that thermal expansions of the spacer and the first andsecond adhesive layers substantially match thermal expansion of theelectrical leads.
 30. The method of claim 27 further comprising couplingthe chip carrier to the mounting structure with electrical leads,wherein the spacer has a first coefficient of thermal expansion CTE₁,wherein the leads have a second coefficient of thermal expansion CTE₂,wherein the first and second adhesive layers have a third coefficient ofthermal expansion CTE₃, and wherein CTE₁<CTE₂<CTE₃.
 31. The method ofclaim 27 wherein the chip carrier and the spacer are both ceramic. 32.The method of claim 27 wherein the first and second adhesive layers areepoxy.
 33. The method of claim 32 wherein the chip carrier and thespacer are both ceramic.
 34. The method of claim 25 wherein the mountingstructure is a printed circuit board.
 35. The method of claim 25 whereinthe spacer is ceramic.
 36. An assembly comprising: a chip carrier; amounting structure; leads electrically coupled to the chip carrier andto the mounting structure; and, a force diverter mechanically coupled tothe chip carrier and to the mounting structure, wherein the forcediverter is arranged to divert force generated by the chip carrier fromthe leads and to the mounting structure.
 37. The assembly of claim 36wherein the force diverter is between the chip carrier and the mountingstructure.
 38. The assembly of claim 37 wherein the force diverter isselected so that thermal expansion of the force diverter substantiallymatches thermal expansion of the leads.
 39. The assembly of claim 36wherein the force diverter is selected so that thermal expansion of theforce diverter substantially matches thermal expansion of the leads.